The present invention relates in general to semiconductor integrated circuit devices and methods of fabrication thereof; and, more particularly, the invention relates to useful techniques for application to semiconductor integrated circuit devices having circuit element isolation grooves, with an insulative film buried within a groove, as formed in a semiconductor substrate.
With an increase in miniaturization or reduction in the size of semiconductor devices for use as on-chip circuit elements, a new element isolation technique has been employed in lieu of prior known local oxidation of silicon (LOCOS) methods. This element isolation technique is one that embeds or buries a silicon oxide film within a groove formed in a semiconductor substrate to thereby form more than one element isolation groove. This technique is also known as the shallow trench isolation (STI) process.
To form an element isolation groove, the process starts with a step of applying thermal processing to the semiconductor substrate (simply referred to as a “substrate” hereinafter) for fabrication of a thin silicon oxide film (also called a pad oxide film) on or above its surface. This pad oxide film is formed for purposes of relaxation of stresses being applied to the substrate which occur during baking for densification of the oxide silicon film buried within the groove, which is carried out at a later step, and also for protection of active regions during removal of a silicon nitride film that is used as a mask for oxidation.
Next, the process has a step of depositing a silicon nitride film at an upper part of the pad oxide film using chemical vapor deposition (CVD) techniques and then remove portions of the silicon nitride film which reside in element isolation regions by etching using a patterned photoresist film as a mask. This silicon nitride film is used as a mask during formation of a groove(s) through etching of the substrate along with a protective film for protection of its underlying substrate surface against oxidation.
Next, after having formed a groove in the substrate by dry etching using the silicon nitride film as a mask, the substrate is thermally oxidized to thereby fabricate a thin silicon oxide film on the inner walls of the groove. This silicon oxide film is formed for purposes of removal of etching damage occurring at the groove inner walls and also stress relaxation of a silicon oxide film to be buried within the groove at a later step.
Next, after having deposited a silicon oxide film by CVD over the substrate to bury it within the groove, the substrate is thermally processed to thereby densify this silicon oxide film. This densification is for effecting improvement in the film quality of the silicon oxide film buried within the groove.
Next, the process has a step of removing the silicon oxide film overlying the silicon nitride film by chemical-mechanical polishing (CMP) techniques causing the silicon oxide film to remain within the groove, thus completing more than one element isolation groove. Thereafter, the silicon nitride film that has been used as a mask during formation of the groove in the substrate is removed by wet etch techniques, thus forming, in active regions, semiconductor circuit elements, such as metal insulator semiconductor field effect transistors (MISFETs).
Unfortunately, it has been pointed out that the element isolation groove as formed by the above-discussed methodology suffers from degradation in device characteristics. This can occur due to a mechanism which will be described as follows. At several thermal oxidation process steps during fabrication of semiconductor elements in active regions, oxidizing agents or oxidizers, such as oxygen and water components in the atmosphere, behave to invade the inside of an element isolation groove and then oxidize the inner walls thereof, resulting in formation of a silicon oxide film. Due to thermal volume expansion of such silicon oxide film, the active region is subjected to a compressive stress force. This stress application can result in creation of unwanted crystal defects and/or dislocations at a portion of the substrate in the active region, causing the device characteristics to degrade. In view of the fact that the compressive stress being applied to the active region by oxidation of the isolation groove inner walls increases with a decrease in isolation groove width, resulting from a decrease in the feature size of on-chip semiconductor devices, this problem is a serious bar to successful achievement of miniaturization or reduction in the size of the semiconductor devices.
Another problem associated with the above-stated element isolation groove, as has been reported to date, is that a drain current can rush to flow even upon application of a low gate voltage. This is called the “kink” or “hump” characteristics among experts in the semiconductor device art. This problem occurs due to a mechanism which will be described as follows. The silicon oxide film buried in a groove is etched away through more than two hydrofluoric-acid cleaning process steps to be carried out during formation of a semiconductor circuit element in an active region, resulting in a portion of the silicon oxide film at an element isolation groove edge being retrograded or “recessed” downwardly, which in turn causes a gate insulating film, that has been formed over a substrate surface portion of the active region, to locally decrease in thickness. This local thinning of such gate insulating film leads to undesired drain current flow even upon application of a low gate voltage.
One prior known approach to suppressing oxidation in the inner walls of element isolation grooves is to fabricate a thin silicon nitride film along the isolation groove inner walls in a way as taught, for example, in U.S. Pat. No. 5,447,884.
In addition, JP-A-2000-31267 discloses therein a remedy for formation of an unwanted groove at the outer periphery of an element isolation groove due to simultaneous etching of an oxidation-preventing silicon nitride film formed on isolation groove inner walls during removal by wet etching of a mask-use silicon nitride film that is used for formation of grooves in a substrate, wherein the remedy employs a technique for increasing its etching rate by doping, through ion implantation, a chosen impurity into the silicon nitride mask to thereby damage it.
JP-A-2000-306990 discloses therein a remedy for preventing the silicon nitride film within an element isolation groove from being recessed due to unintentional etching during removal by wet etching of a pad oxide film that has been formed beneath the mask-use silicon nitride film, wherein the remedy makes use of a technique for applying thermal processing to the silicon oxide film within the isolation groove in a nitride gaseous atmosphere after having etched away the silicon nitride mask and yet prior to removal of the pad oxide film.
Considering the technology from a different viewpoint from the problem stated above, JP-A-8-227938 discloses a remedy for precluding undesired etching of the silicon oxide film within an element isolation groove, that occurs as a result of overlapping of a portion of a through-going hole with the isolation groove due to possible mask positioning/alignment deviation during formation of the through-hole deep enough to reach its underlying substrate, by etching of a silicon oxide film that has been deposited over the substrate, by use of a technique for forming a silicon nitride film overlying the silicon oxide film within the isolation groove, to thereby use this silicon nitride film as an etching stopper during formation of the through-hole.